1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a semiconductor device that can be easily produced at low cost and that can achieve communication with low power consumption.
2. Description of the Related Art
With the popularization of electronic devices, a layering technique and a chip wiring technique have been proposed which allow a multichip package or a system-in package (SIP) including stacked multichip modules (MCMs) to be obtained at low cost.
FIG. 1 shows an example of a configuration of a known multichip module. In this multichip module, a silicon interposer 1 and a silicon interposer 21 are combined with each other. Chips 5 are mounted on a first surface 2 of the silicon interposer 1 with bumps 4 disposed therebetween, and similarly, chips 25 are mounted on a first surface 22 of the silicon interposer 21 with bumps 24 disposed therebetween. Through holes 6 are provided between the first surface 2 and a second surface 3 of the silicon interposer 1, and through holes 26 are provided between the first surface 22 and a second surface 23 of the silicon interposer 21. The through holes 6 and the through holes 26 are connected by bumps 7. Communication between the chips 5 on the silicon interposer 1 and the chips 25 on the silicon interposer 21 is conducted via a pattern provided on the silicon interposer 1, the through holes 6 of the silicon interposer 1, the bumps 7, the through holes 26 of the silicon interposer 21, and a pattern provided on the silicon interposer 21.
However, when the through holes are formed, it is necessary to add a new process and to form electrodes on the second surfaces of the silicon interposers. Moreover, it is difficult to form fine through holes.
Accordingly, Nikkei Electronics, Oct. 10, 2005, pp. 92-99 discloses communication utilizing capacitance coupling, as shown in FIG. 2A. In FIG. 2A, an electrode 41 is provided on a first surface 2 (a surface on which chips 5 are mounted) of a silicon interposer 1, and similarly, an electrode 51 is provided on a first surface (a surface on which chips 25 are mounted) of an interposer 21. The first surface 2 of the silicon interposer 1 and the first surface 22 of the silicon interposer 21 are aligned so that the electrode 41 and the electrode 51 face each other. Communication between the chips 5 on the first surface 2 of the silicon interposer 1 and the chips 25 on the first surface 22 of the silicon interposer 21 is conducted by using electrostatic induction between the electrodes 41 and 51.